Semiconductor device, method of fabricating the same, and apparatus used in fabrication thereof

ABSTRACT

A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper impurity regions, metal silicide layers between the metal electrodes and the upper impurity regions, and a lower impurity region in a lower portion of the substrate. A method of fabricating the semiconductor device and an apparatus used in fabricating the semiconductor device is also provided.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No.15/635,725, filed on Jun. 28, 2017, which is a divisional of U.S.application Ser. No. 14/845,951, filed on Sep. 4, 2015, and issued asU.S. Pat. No. 9,735,016 on Aug. 15, 2017, which claims priority under 35U.S.C. § 119 to Korean Patent Application No. 10-2014-0160058, filed onNov. 17, 2014, in the Korean Intellectual Property Office, the entirecontents of each of the above-referenced applications are herebyincorporated by reference.

BACKGROUND

Inventive concepts relate to a method of fabricating a semiconductordevice, and more particularly, to a semiconductor device, a method offabricating the same, and an apparatus used in fabrication thereof.

In fabrication of semiconductor devices, contact technologies forobtaining low contact resistance values may be required to produce highperformance semiconductor devices. A metal silicidation process has beenwidely used in formation of contact structures having a low contactresistance value. For example, a metal layer such as a cobalt (Co) layeror a nickel (Ni) layer may be deposited on a silicon substrate or apolysilicon layer and the metal layer may be annealed to form a cobaltsilicide (CoSi_(x)) layer or a nickel silicide (NiSi_(x)) layer. Inaddition, after impurity ions are implanted into active regions of asilicon substrate to form source/drain regions, the impurity ions in thesource/drain regions may be activated to reduce contact resistancevalues of the source/drain regions.

SUMMARY

Inventive concepts relate to semiconductor devices, methods offabricating the same, and/or apparatuses used in fabrication thereof.

According to example embodiments of inventive concepts, a semiconductordevice includes a substrate, upper impurity regions in upper portions ofthe substrate, metal electrodes electrically connected to the upperimpurity regions, metal silicide layers between the metal electrodes andthe upper impurity regions, and a lower impurity region in a lowerportion of the substrate.

In example embodiments, the substrate may be a P-type substrate, theupper impurity regions may include NMOS impurity regions of an NMOStransistor, and the NMOS impurity regions may include a P-type heavilydoped region in the substrate and an N-type halo region under the P-typeheavily doped region.

In example embodiments, the substrate may be a P-type substrate, thesubstrate may include an N-type well, the upper impurity regions mayinclude P-type heavily doped source and drain regions of a PMOStransistor and N-type heavily doped source and drain regions of an NMOStransistor. The PMOS transistor may include an N-type heavily doped bodycontact region in the N-type well. The NMOS transistor may include aP-type heavily doped body contact region in the substrate and an N-typehalo region under the P-type heavily doped region in the substrate. Thelower impurity region may be a P-type heavily doped lower impurityregion.

In example embodiments, the semiconductor device may further includeglobal buried contacts (GBCs) respectively on the upper impurityregions. The semiconductor device may be a dynamic random access memory(DRAM) device. The metal silicide layers may be between the GBCs and themetal electrodes.

In example embodiments, the semiconductor device may be a logic device,the upper impurity regions may include source/drain regions and bodycontact regions. The metal silicide layers may correspond to interfaciallayers between the source/drain regions and the metal layers as well asbetween the body contact regions and the metal layers.

According to example embodiments of inventive concepts, a method offabricating a semiconductor device includes forming a metal layer on anactive layer, applying a first annealing process to the metal layer andthe active layer to form a metal silicide layer, and concentratingimpurity ions in the active layer at an interface between the activelayer and the metal silicide layer by creating an electric field acrossthe active layer and the metal silicide layer.

In example embodiments, the first annealing process and theconcentrating impurity ions may be performed at the same time such thatthe electric field is created while the first annealing process isapplied.

In example embodiments, the concentrating impurity ions may includeapplying a second annealing process to the active layer and the metalsilicide layer after the first annealing process. The electric field maybe created during the second annealing process.

In example embodiments, the active layer and the metal layer may contactother to define a Schottky junction therebetween. The concentratingimpurity ions may include applying a voltage that is equal to or lowerthan 10 volts to the Schottky junction in order to create the electricfield.

In example embodiments, the first annealing process may include theconcentrating impurity ions by creating the electric field across theactive layer and the metal silicide layer or the concentrating impurityions may include a second annealing process that is formed after thefirst anneal process and includes the creating the electric field acrossthe active layer and the metal silicide layer. The first and secondannealing processes may be performed at a temperature about 150 degreesCelsius to about 1100 degrees Celsius.

In example embodiments, the method may further include implantingimpurity ions into the active layer. The implant impurity ions into theactive layer may be performed before the forming the metal layer, whilethe applying the first annealing process is performed, or after theapplying the first annealing process is performed.

In example embodiments, the implanting the impurity ions into the activelayer may include using an in-situ doping process while the active layeris formed if the impurity ions are implanted before the metal layer isformed.

In example embodiments, the concentrating impurity ions in the activelayer may include concentrating the impurity ions at an interfacebetween the active layer and the metal silicide layer using an ionimplantation process and a second annealing process that are performedafter the applying the first annealing process.

In example embodiments, the method may further including forming apolysilicon layer on the active layer before the forming the metallayer, and implanting impurity ions into the polysilicon layer after theapplying the first annealing process. The semiconductor device may be aDRAM device. The forming the metal layer may include forming the metallayer on the polysilicon layer. The concentrating the impurity ions mayinclude creating the electric field during the implanting the impurityions into the polysilicon layer or during a second annealing processthat is performed after the implanting the impurity ions into thepolysilicon layer.

In example embodiments, the polysilicon layer may constitute a globalburied contact (GBC) of the DRAM device, and the metal silicide layermay correspond to an interfacial layer between the GBC and the metallayer.

In example embodiments, the method may further include implantingimpurity ions into the active layer before the forming the metal layer.The semiconductor device may be a logic device including a CMOS circuit.The concentrating impurity ions may include creating the electric fieldduring the applying the first annealing process or while a secondannealing process is performed after the applying the first annealingprocess.

In example embodiments, the metal silicide layer may be an interfaciallayer between the metal layer and the source/drain regions.

According to example embodiments of inventive concepts, a method offabricating a semiconductor device includes forming an active layer on asubstrate, forming a metal layer on the active layer, forming an upperelectrode on a top surface of the substrate including the active layerand the metal layer, forming a lower electrode on a bottom surface ofthe substrate to provide ohmic contact between the lower electrode andthe substrate, and annealing the substrate including the lower electrodeand the lower electrode while an electric field is created between theupper electrode and the lower electrode.

In example embodiments, the method may further include forming apolysilicon layer on the active layer before the forming the metallayer, and applying a first annealing process to the polysilicon layerand the metal layer to form a metal silicide layer before the formingthe upper electrode.

In example embodiments, the method may further include implantingimpurity ions into the polysilicon layer before the forming the metallayer or after the applying the first annealing process. The impurityions may be concentrated at an interface between the polysilicon layerand the metal silicide layer during the annealing the substrate whilethe electric field is created between the upper electrode and the lowerelectrode.

In example embodiments, the method may further include implantingimpurity ions into the active layer before the forming the metal layer.The annealing the substrate while the electric field is created mayinclude forming a metal silicide between the active layer and the metallayer, and concentrating the impurity ions in the active layer at aninterface between the active layer and the metal silicide layer.

In example embodiments, the forming the active layer and the metal layermay include forming a body contact region in the substrate and forming ahalo region under the body contact region. The forming the lowerelectrode may include forming a heavily doped region in a lower portionof the substrate.

In example embodiments, the substrate may be a P-type substrate. Theactive regions may include PMOS impurity regions of a PMOS transistorand NMOS impurity regions of an NMOS transistor. The PMOS impurityregions may include an N-type well in the substrate, an N-type heavilydoped body contact region in the N-type well, and P-type heavily dopedsource and drain regions n the N-type well. The NMOS impurity regionsmay include a P-type heavily doped body contact region in the substrate,an N-type halo region under the P-type heavily doped region in thesubstrate, and N-type heavily doped source and drain regions in thesubstrate. The lower electrode may further include a P-type heavilydoped lower impurity region in a lower portion of the substrate.

In example embodiments, the upper electrode may include a titanium (Ti)layer and a titanium nitride (TiN) layer or a Ti/TiN layer and atungsten (W) layer. The lower electrode may include a Ti/TiN layer.

According to example embodiments of inventive concepts, an apparatusthat may be used in fabricating a semiconductor device is provided. Theapparatus includes a supporter configured to support a wafer, atemperature/voltage controller configured to control a temperature and avoltage applied to the wafer, a heat source over the supporter, the heatsource being configured to emit heat toward the wafer and be controlledby the temperature/voltage controller, a power source configured toapply a voltage to the wafer and be controlled by thetemperature/voltage controller, an upper lead probe connected to thepower source and configured to contact a top surface of the wafer, and alower lead probe connected to a ground terminal of the power source andconfigured to contact a bottom surface of the wafer.

In example embodiments, the wafer may include a lower electrode on a topsurface thereof and an upper electrode connected to a bottom surfacethereof, the upper lead probe may contact the lower electrode, and thelower lead probe may contact the upper electrode.

In example embodiments, the temperature/voltage controller may beconfigured to apply programmed heat and voltage to the wafer through theheat source and the power source in a concurrent time domain.

In example embodiments, a temperature sensor may be under the wafer. Thetemperature/voltage controller may be configured to control an operationof the heat source based on temperature information that is outputtedfrom the temperature sensor.

In example embodiments, the apparatus may be configured to concentrateimpurity ions in the wafer at an interface between the active layer anda metal silicide layer in the wafer, based on emitting heat from theheat source and applying the voltage generated from the power source tothe wafer.

According to example embodiments of inventive concepts, a method offabricating a semiconductor device includes forming a conductive layeron an active layer; and performing an annealing process while applying avoltage across the active layer and concentrating impurity ions at aninterface between an impurity region of the active layer and theconductive layer.

In example embodiments, the forming the conductive layer on the activelayer may include forming a metal layer on the active layer andtransforming at least a part of the metal layer to a metal silicidelayer on the active layer, and the performing the annealing processwhile applying the voltage across the active layer and concentrating theimpurity ions may include concentrating the impurity ions at aninterface between the impurity region of the active layer and the metalsilicide layer.

In example embodiments, the forming the conductive layer on the activelayer may include forming a metal layer on the active layer, and theperforming the annealing process while applying the voltage across theactive layer and concentrating the impurity ions may includetransforming at least part of the metal layer to a metal silicide layerduring the annealing process.

In example embodiments, the active layer and the conductive layer maycontact each other to define a Schottky junction therebetween, and theperforming the annealing process while applying the voltage across theactive layer and concentrating the impurity ions may include creating anelectric field across the Schottky junction based on applying thevoltage to the Schottky junction in a range that is equal to or lowerthan 10.

In example embodiments, the annealing process is performed at atemperature of about 150 degrees Celsius to about 1100 degrees Celsius.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other features of inventive concepts will be apparentfrom the more particular description of non-limiting embodiments ofinventive concepts, as illustrated in the accompanying drawings in whichlike reference characters refer to like parts throughout the differentviews. The drawings are not necessarily to scale, emphasis instead beingplaced upon illustrating principles of inventive concepts. In thedrawings:

FIGS. 1A and 1B illustrate a cross-sectional view of a semiconductordevice and a graph of a voltage versus a distance to explain a principleof an annealing process accompanied with electric field used infabrication of a semiconductor device according to example embodiments;

FIG. 2 is a schematic diagram illustrating an annealing processaccompanied with electric field used in a fabrication method of asemiconductor device according to example embodiments;

FIGS. 3, 4 and 5 are process flowcharts illustrating methods offabricating semiconductor devices according to example embodiments usingan annealing process accompanied with electric field;

FIGS. 6A, 6B, 6C and 6D are cross-sectional views illustrating a methodof fabricating a semiconductor device shown in FIG. 5;

FIGS. 7 and 8 are process flowcharts illustrating methods of fabricatingsemiconductor devices according to example embodiments using anannealing process accompanied with electric field;

FIGS. 9A, 9B and 9C are cross-sectional views illustrating a method offabricating a semiconductor device shown in FIG. 8;

FIGS. 10 and 11 are process flowcharts illustrating methods offabricating semiconductor devices on a substrate of a wafer levelaccording to example embodiments using an annealing process accompaniedwith electric field;

FIG. 12 is a cross-sectional view illustrating a semiconductor device ofa wafer level to which electric field is applied according to exampleembodiments;

FIG. 13 is an equivalent circuit diagram illustrating junctions in thesemiconductor device shown in FIG. 12;

FIG. 14 is a cross-sectional view illustrating a semiconductor devicefabricated by a CMOS process according to example embodiments;

FIG. 15A is a plan view illustrating a dynamic random access memory(DRAM) device according to example embodiments;

FIGS. 15B, 15C and 15D are cross-sectional views taken along lines I-I′,II-II′ and III-III′ of FIG. 15A, respectively;

FIGS. 16A and 16B are schematic diagrams illustrating a DRAM deviceaccording to example embodiments;

FIGS. 17A and 17B are cross-sectional views illustrating a principle ofa silicide as dopant source (SADS) technology used in fabrication ofsemiconductor devices according to example embodiments;

FIG. 18 a schematic view illustrating an apparatus used in fabricationof semiconductor devices according to example embodiments; and

FIG. 19 is a graph illustrating a voltage and a temperature applied to awafer loaded into the apparatus shown in FIG. 18.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Example embodiments will now be described more fully with reference tothe accompanying drawings, in which some example embodiments are shown.Example embodiments, may, however, be embodied in many different formsand should not be construed as being limited to the embodiments setforth herein; rather, these example embodiments are provided so thatthis disclosure will be thorough and complete, and will fully convey thescope of example embodiments of inventive concepts to those of ordinaryskill in the art. In the drawings, the thicknesses of layers and regionsare exaggerated for clarity. Like reference characters and/or numeralsin the drawings denote like elements, and thus their description may beomitted.

It will be understood that when an element or layer is referred to asbeing “connected to” or “coupled to” another element or layer, theelement or layer may be directly connected or coupled to the otherelement or layer, or intervening elements or layers may be present. Incontrast, when an element is referred to as being “directly connected”or “directly coupled” to another element, there are no interveningelements present. Other words used to describe the relationship betweenelements or layers should be interpreted in a like fashion (e.g.,“between” versus “directly between,” “adjacent” versus “directlyadjacent,” “on” versus “directly on”). As used herein the term “and/or”includes any and all combinations of one or more of the associatedlisted items.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of exampleembodiments. As used herein, the singular forms “a,” “an” and “the” areintended to include the plural forms as well, unless the context clearlyindicates otherwise. It will be further understood that the terms“comprises”, “comprising”, “includes” and/or “including,” if usedherein, specify the presence of stated features, integers, steps,operations, elements and/or components, but do not preclude the presenceor addition of one or more other features, integers, steps, operations,elements, components and/or groups thereof. Expressions such as “atleast one of,” when preceding a list of elements, modify the entire listof elements and do not modify the individual elements of the list.

Example embodiments are described herein with reference tocross-sectional illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of exampleembodiments. As such, variations from the shapes of the illustrations asa result, for example, of manufacturing techniques and/or tolerances,are to be expected. Thus, example embodiments should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. Thus, the regions illustrated in the figures areschematic in nature and their shapes are not intended to illustrate theactual shape of a region of a device and are not intended to limit thescope of example embodiments.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which example embodiments belong. Itwill be further understood that terms, such as those defined incommonly-used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of the relevant artand will not be interpreted in an idealized or overly formal senseunless expressly so defined herein.

FIGS. 1A and 1B illustrate a cross-sectional view of a semiconductordevice and a graph of a voltage versus a distance to explain a principleof an annealing process accompanied with electric field used infabrication of a semiconductor device according to example embodiments.

Referring to FIG. 1A, an annealing process accompanied with electricfield may be used in fabrication of a semiconductor device 100 includinga contact structure comprised of a metal silicide layer 140 and asilicon layer 130. The semiconductor device 100 may include the siliconlayer 130 heavily doped with N-type impurities, the metal silicide layer140 disposed on a first surface S1 of the silicon layer 130, and anohmic contact layer 110 disposed on a second surface S2 of the siliconlayer 130 opposite to the metal silicide layer 140. The silicon layer130 may include a depletion region 130 b contacting the metal silicidelayer 140 and a non-depletion region 130 a contacting the ohmic contactlayer 110. Accordingly, the first surface S1 of the silicon layer 130may correspond to an interface between the metal silicide layer 140 andthe depletion region 130 b, and the second surface S2 of the siliconlayer 130 may correspond to an interface between the ohmic contact layer110 and the non-depletion region 130 a.

Meanwhile, the ohmic contact layer 110 may be formed on the secondsurface S2 of the silicon layer 130 so that most of a reverse biasedvoltage Vr applied between the metal silicide layer 140 and the siliconlayer 130 is applied across the depletion region 130 b. If it is assumedthat most of the reverse biased voltage Vr between the metal silicidelayer 140 and the silicon layer 130 is applied across the depletionregion 130 b, a Schottky barrier height (SBH) of the metal silicidelayer 140 and the silicon layer 130 may increase by the reverse biasedvoltage Vr and a width of the depletion region 130 b may also increase,as illustrated in the graph of FIG. 1B.

As such, if the reverse biased voltage Vr is applied between the metalsilicide layer 140 and the silicon layer 130 using the ohmic contactlayer 110, electric field between the metal silicide layer 140 and thesilicon layer 130 may increase to concentrate dopants at an interfacebetween the metal silicide layer 140 and the silicon layer 130. Forexample, when a width of the depletion region 130 b is 5 nanometers andthe reverse biased voltage Vr applied between the metal silicide layer140 and the silicon layer 130 is 0.5 volts, electric field of about1×10⁶/cm may be created across the depletion region 130 b if it isassumed that most of the reverse biased voltage Vr is applied across thedepletion region 130 b. Thus, dopants corresponding to N-type impurityions such as phosphorus (P) ions or arsenide (As) ions in the siliconlayer 130 may be concentrated at an interface between the metal silicidelayer 140 and the silicon layer 130. Meanwhile, since electrons having arelatively low mass pass through the depletion region 130 b at a highspeed, the interaction between the dopants and the electrons may beneglected and may not cause leakage current generated due to theelectric field.

Ionized donor atoms (e.g., donor ions) having positive net charges inthe depletion region 130 b may be drifted by a negative biascorresponding to the reverse biased voltage Vr to move toward theinterface between the metal silicide layer 140 and the silicon layer130. Thus, a dopant concentration at the interface between the metalsilicide layer 140 and the silicon layer 130 may increase. In addition,the ionized donor atoms may be more stably activated in the siliconlayer 130 under the negative bias condition. Accordingly, a contactresistance value between the metal silicide layer 140 and the siliconlayer 130 may be reduced. Meanwhile, if the ionized donor atoms in thedepletion region 130 b are accumulated at the interface between themetal silicide layer 140 and the silicon layer 130, donors in thenon-depletion region 130 a may be supplied into the depletion region 130b.

In order to reduce a contact resistance value between a metal layer anda silicon layer, dopants should be stably activated at an interfacebetween the metal layer and the silicon layer and an abrupt junctionshould be formed at the interface between the metal layer and thesilicon layer. The abrupt junction may be formed by confining a heavilydoped impurity region in the vicinity of the interface between the metallayer and the silicon layer. The dopants may be more activated at a hightemperature. However, if the temperature rises up, diffusion of thedopants may also increase. In such a case, it may be difficult toconcentrate the dopants at the interface between the metal layer and thesilicon layer. Accordingly, a metal silicide layer may be generallyformed to reduce the contact resistance value of the silicon layer.Nevertheless, there may be a limitation in reducing the contactresistance value of the silicon layer because a junction location variesaccording to a growth of the metal silicide layer. In fabrication of asemiconductor device, the metal silicide layer may be formed to reducean eternal resistance value except a channel resistance value of ametal-oxide-semiconductor (MOS) transistor. However, if the metalsilicide layer is used in fabrication of a semiconductor device,deviation of a resistance value may increase due to external growth andinhomogeneous phases of the metal silicide layer.

Meanwhile, the dopants may be excessively implanted into a silicon layerto form source/drain regions and to reduce a contact resistance of thesource/drain regions. That is, the dopants may be super-saturated toreduce a contact resistance of the source/drain regions. However, insuch a case, diffusion by heat budget and de-activation of the dopantsmay be generated to degrade performance of a semiconductor device. Forexample, in fabrication of DRAM devices, if dopants in a silicon layerare super-saturated to form a global buried contact (GBC) structurecomprised of a cobalt silicide (CoSi₂) layer and a polysilicon layer,the morphology of the polysilicon layer may be degraded and a gateinduced drain leakage (GIDL) characteristic of cell transistors in theDRAM devices may also be degraded. As a result, a refresh interval timetREF of the DRAM devices may be reduced to degrade a refreshcharacteristic of the DRAM devices. Further, in fabrication of logicdevices, if dopants in a silicon layer are super-saturated to form acontact structure comprised of a nickel silicide (NiSi) layer and thesilicon layer, a spreading resistance value Rspr may increase and anoff-current value of MOS transistors may also increase. As a result, theMOS transistors may suffer from a short channel effect.

According to example embodiments, an annealing process accompanied withelectric field may be used in fabrication of a semiconductor device. Theannealing process accompanied with electric field may concentratedopants at an interface between a metal silicide layer and a siliconlayer and may stably activate the concentrated dopants to reduce acontact resistance value between the metal silicide layer and thesilicon layer. Accordingly, the annealing process accompanied withelectric field may reduce problems that occur due to high temperature ofthe conventional annealing process and super-saturation of dopants. Inaddition, if the annealing process accompanied with electric field isused in fabrication of semiconductor devices, a thickness of the metalsilicide layer may be reduced.

FIG. 2 is a schematic diagram illustrating an annealing processaccompanied with electric field used in a fabrication method of asemiconductor device according to example embodiments.

Referring to FIG. 2, an annealing process accompanied with electricfield may be performed at a wafer level. That is, the annealing processaccompanied with electric field may be applied to not respectivesemiconductor devices but an entire wafer including a plurality ofsemiconductor devices.

Specifically, in order to perform the annealing process accompanied withelectric field, a wafer including a semiconductor device 100 a may beloaded into an annealing chamber 1100 and a power source 1500 may beconnected to the semiconductor device 100 a to create electric fieldacross the semiconductor device 100 a. The semiconductor device 100 amay include an ohmic contact layer 110, a substrate 120, an active layer130, a metal silicide layer 140 and an upper electrode 150 which aresequentially stacked.

The ohmic contact layer 110 may be disposed on a bottom surface of thesubstrate 120 to include a lower electrode (112 of FIG. 12) and aheavily doped region (114 of FIG. 12) disposed between the substrate 120and the lower electrode 112. In example embodiments, the ohmic contactlayer 110 may be comprised of only the lower electrode 112 and theheavily doped region 114 may be included in the substrate 120 or may beindependently disposed. The ohmic contact layer 110 may be formed sothat most of a voltage provided by the power source 1500 is appliedacross a depletion region 130 b of the active layer 130, as describedwith reference to FIG. 1. If the substrate 120 and the lower electrode112 directly contact each other without the heavily doped region 114, aSchottky junction may be present between the substrate 120 and the lowerelectrode 112 and a portion of a voltage provided by the power source1500 may be applied across the Schottky junction between the substrate120 and the lower electrode 112. In such a case, dopants in thedepletion region 130 b may be insufficiently concentrated at theinterface between the metal silicide layer 140 and the depletion region130 b.

The lower electrode 112 may be formed of a refractory metal layer havingexcellent process compatibility. In addition, the lower electrode 112may be formed to have a single-layered structure or a multi-layeredstructure. For example, the lower electrode 112 may be formed of acombination layer of a titanium (Ti) layer and a titanium nitride (TiN)layer. However, the lower electrode 112 is not limited to a combinationlayer of a titanium (Ti) layer and a titanium nitride (TiN) layer. Theheavily doped region 114 may be a P-type region if the substrate 120 isa P-type substrate. In example embodiments, the heavily doped region 114may be formed by implanting boron atoms into the substrate 120 of aP-type conductivity and may be formed to have an impurity concentrationof at least 1×10¹⁹/cm³. For example, the heavily doped region 114 may beformed to have an impurity concentration of at least the impurity regionmay be formed to have an impurity concentration in a range of at least1×10¹⁹/cm³ to at least 1×10²⁰/cm³. The dopant of the heavily dopedregion 114 is not limited to boron atoms. The heavily doped region 114may be an N-type region if the substrate 120 is an N-type substrate.

The substrate 120 may be a semiconductor layer. For example, thesubstrate 120 may be a single crystalline silicon layer, apolycrystalline silicon layer (also, referred to as a polysiliconlayer), or an amorphous silicon layer. However, the substrate 120 is notlimited to a silicon substrate. For example, in example embodiments, thesubstrate 120 may include a Group IV material such as germanium (Ge), aGroup IV-IV compound material such as silicon germanium (SiGe) orsilicon carbide (SiC), or a Group III-V compound material such asgallium arsenide (GaAs), indium arsenide (InAs) or indium phosphide(InP). The substrate 120 may be a bulk substrate, for example, a silicon(Si) bulk substrate or a silicon germanium (SiGe) bulk substrate.Alternatively, the substrate 120 is not limited to a bulk substrate. Forexample, the substrate 120 may be an epitaxial wafer, a polished wafer,or an annealed wafer.

The substrate 120 may be a P-type substrate doped with P-type impuritiesor an N-type substrate doped with N-type impurities. For example, in anon-limiting example, the substrate 120 may be a P-type substrate.

The active layer 130 may be an impurity region that is formed byimplanting P-type impurities or N-type impurities into the substrate120. In a non-limiting example, the active layer 130 may be an N-typeimpurity region that is formed by implanting N-type impurities into thesubstrate 120 having a P-type conductivity. This N-type impurity region130 may act as an N-type source/drain region (134 sd of FIG. 12)included in a complementary MOS (CMOS) device. As illustrated in FIG. 2,the depletion region 130 b may be formed in the active layer 130 tocontact the metal silicide layer 140.

The metal silicide layer 140 may be disposed on the active layer 130 toprovide a Schottky junction between the metal silicide layer 140 and theactive layer 130. The metal silicide layer 140 may be, for example, anickel silicide (NiSi_(x)) layer. The metal silicide layer 140 may beformed by depositing a metal layer such as nickel layer (or a cobaltlayer) on the active layer 130 and by annealing the metal layer to reactthe metal layer with the active layer 130.

The upper electrode 150 may be formed of a refractory metal layer havingan excellent process compatibility, like the lower electrode 112. Inaddition, the upper electrode 150 may be formed to have a single-layeredstructure or a multi-layered structure. For example, the upper electrode150 may be formed of a combination layer of a titanium (Ti) layer and atitanium nitride (TiN) layer. The upper electrode 150 may furtherinclude a tungsten layer disposed on the Ti/TiN layer. The upperelectrode 150 may be divided into a plurality of metal patterns afterelectric field is applied to the wafer including the semiconductordevices 100 a, and each of the plurality of metal patterns may be usedas a metal electrode through which an electric signal or a voltage isapplied to one among the plurality of semiconductor devices.

The wafer including the semiconductor device 100 a having theaforementioned structure may be loaded into the annealing chamber 1100,and the ohmic contact layer 110 and the upper electrode 150 may beelectrically connected to both output terminals of the power source 1500to perform the annealing process accompanied with electric field. Thepower source 1500 may be electrically connected to the ohmic contactlayer 110 and the upper electrode 150 so that a negative bias is appliedto the Schottky junction between the metal silicide layer 140 and theactive layer 130. For example, if the active layer 130 is an N-typeimpurity region, the upper electrode 150 may be electrically connectedto a negative electrode of the power source 1500 and the ohmic contactlayer 110 may be electrically connected to a positive electrode of thepower source 1500.

As a result of the annealing process accompanied with electric field,dopants in the active layer 130 may be concentrated at an interfacebetween the metal silicide layer 140 and the active layer 130. Forexample, if the active layer 130 is an N-type impurity region, donorions (e.g., phosphorus ions or arsenide ions) having positive netcharges may be concentrated at the interface between the metal silicidelayer 140 and the active layer 130. Thus, a dopant concentration at theinterface between the metal silicide layer 140 and the active layer 130may increase, and the dopants may be stably activated. Accordingly, acontact resistance value between the metal silicide layer 140 and theactive layer 130 may be reduced.

FIGS. 3, 4 and 5 are process flowcharts illustrating methods offabricating semiconductor devices according to example embodiments usingan annealing process accompanied with electric field.

Referring to FIG. 3, a method of fabricating a semiconductor deviceaccording to example embodiments may include forming a metal layer on animpurity region in a substrate (see operation S110). The substrate maybe a P-type substrate or an N-type substrate. The impurity region may bea heavily doped region that is formed by implanting impurity ions intothe substrate and may correspond to the silicon layer or the activelayer indicated by reference numeral 130 in FIG. 1A or 2. For example,the impurity region may be a source/drain region that is formed byimplanting impurity ions into the substrate. In such a case, theimpurity region may be formed to have an impurity concentration of atleast 1×10²⁰/cm³. For example, the impurity region may be formed to havean impurity concentration in a range of at least 1×10²⁰/cm³ to at least1×10²¹/cm³. The metal layer may be formed of, for example, a cobaltlayer or a nickel layer. In example embodiments, a Ti/TiN barrier layermay be additionally formed on the metal layer.

After forming the metal layer, a first annealing process may be appliedto the metal layer to form a metal silicide layer (see operation S120).The first annealing process may be performed at a temperature of about150 degrees Celsius to about 1100 degrees Celsius. In other words, atemperature of the annealing chamber 1100 may be in a range about 150degrees Celsius to about 1100 degrees Celsius when the first annealingprocess is applied to the metal layer to form a metal silicide layer.However, a temperature of the first annealing process is not limited tothe aforementioned range. After the metal silicide layer is formed,unreacted metal may be removed.

Subsequently, impurity ions may be concentrated at an interface betweenthe impurity region and the metal silicide layer using a secondannealing process and electric field (see a step 130). The secondannealing process may also be performed at a temperature of about 150degrees Celsius to about 1100 degrees Celsius. In other words, atemperature of the annealing chamber 1100 may be in a range about 150degrees Celsius to about 1100 degrees Celsius during the secondannealing process. However, a temperature of the second annealingprocess is not limited to the aforementioned range. A temperature usedin the first annealing process may be the same as or different than thetemperature used in the second annealing process. For example, atemperature used in the first annealing process may be greater than thetemperature of the second annealing process, equal to the temperature ofthe second annealing process, or less than the temperature of the secondannealing process. A voltage, which is equal to or lower than 10 voltsmay be applied between the impurity region and the metal silicide layerto create electric field across the impurity region. For example, avoltage that is greater than or equal to 1 volt and less than or equalor 10 volts may be applied between the impurity region and the metalsilicide layer to create an electric field across the impurity region.The voltage applied between the impurity region and the metal silicidelayer is not limited to the aforementioned voltage range. For example,in example embodiments, the voltage applied between the impurity regionand the metal silicide layer may be higher than 10 volts. The secondannealing process with the electric field may reduce a contactresistance value between the impurity region and the metal silicidelayer, as described with reference to FIG. 1.

The impurity ions concentrated at the interface by the second annealingprocess and the electric field may correspond to impurity ions that areinjected into the impurity region using an in-situ doping process whilethe impurity region is formed or may correspond to other impurity ionsthat are implanted into the impurity region using a separate ionimplantation process after the impurity region is formed. If theimpurity ions are implanted into the impurity region using the separateion implantation process, the separate ion implantation process may beperformed before the metal layer is formed or after the metal silicidelayer is formed. A detailed description of the separate ion implantationprocess will be described with reference to FIGS. 5 and 6 later.

Next, the semiconductor device 100 a arrayed in the wafer may becompletely fabricated using subsequent processes. The subsequentprocesses may include a deposition process, an etch process, a cleaningprocess or the like. The deposition process may include a chemicalvapour deposition (CVD) process, a sputtering process and a spin coatingprocess. The subsequent processes may further include a packagingprocess for attaching the semiconductor device 100 a to a printedcircuit board (PCB) and for encapsulating the semiconductor device 100 awith sealant. In addition, the subsequent processes may further includea test step for evaluating characteristics of the semiconductor device100 a or a semiconductor package including the semiconductor device 100a.

Referring to FIG. 4, a method of fabricating a semiconductor deviceaccording to example embodiments may include forming a metal layer on animpurity region in a substrate (see operation S210). The substrate, theimpurity region and the metal layer may be formed using the same mannersas described with reference to FIG. 3.

After forming the metal layer, an annealing process accompanied withelectric field may be applied to the substrate including the metal layerto form a metal silicide layer and to concentrate impurity ions at aninterface between the impurity region and the metal silicide layer (seeoperation S220). The annealing process may be performed at a temperatureof about 150 degrees Celsius to about 1100 degrees Celsius, like thefirst or second annealing process described with reference to FIG. 3.Moreover, the electric field may be created by applying a voltage, whichis equal to or lower than 10 volts, to a junction between the metallayer and the impurity region.

In example embodiments, the method described with reference to FIG. 4may be different from the method discussed in FIG. 3 in terms of amanner for forming the metal silicide layer and for concentrating theimpurity ions. That is, according to example embodiments, the impurityions may be concentrated at the interface between the impurity regionand the metal silicide layer while the metal silicide layer is formed bythe annealing process accompanied with electric field. Alternatively, inexample embodiments, as described with reference to FIG. 3, the metalsilicide layer may be formed by the first annealing process whereas theimpurity ions may be concentrated by the second annealing processaccompanied with the electric field which is separated from the firstannealing process. Meanwhile, even in a non-limiting example, theimpurity ions concentrated at the interface may correspond to impurityions which are injected into the impurity region using an in-situ dopingprocess while the impurity region is formed or may correspond to otherimpurity ions which are implanted into the impurity region using aseparate ion implantation process after the impurity region is formed.If the impurity ions are implanted into the impurity region using theseparate ion implantation process, the separate ion implantation processmay be performed before the metal layer is formed.

Referring to FIG. 5, a method of fabricating a semiconductor deviceaccording to example embodiments may include forming a metal layer on animpurity region in a substrate (see operation S310). The substrate, theimpurity region and the metal layer may be formed using the same mannersas described with reference to FIG. 3.

After forming the metal layer, a first annealing process may be appliedto the substrate including the metal layer to form a metal silicidelayer (see operation S320). The metal silicide layer may also be formedusing the same manners as described with reference to FIG. 3. Impurityions may then be implanted into the impurity region (see operationS330). Specifically, the impurity ions may be implanted into theimpurity region after forming a material layer on an entire surface ofthe substrate, etching the material layer to expose the impurity region,and selectively implanting the impurity ions into the exposed impurityregion at a desired (and/or alternatively predetermined) dose with adesired (and/or alternatively predetermined) energy using animplantation apparatus.

After implanting the impurity ions, the impurity ions may beconcentrated at an interface between the impurity region and the metalsilicide layer using a second annealing process accompanied withelectric field (see operation S340). The second annealing processaccompanied with the electric field for concentrating the impurity ionsmay be the same as the second annealing process accompanied with theelectric field illustrated in FIG. 3.

FIGS. 6A, 6B, 6C and 6D are cross-sectional views illustrating a methodof fabricating a semiconductor device shown in FIG. 5.

Referring to FIG. 6A, a metal layer 282 may be formed on a semiconductorlayer 280. For example, the semiconductor layer 280 may be a polysiliconlayer formed on an impurity region. Specifically, the impurity regionacting as a source/drain region may be formed by implanting impurityions into a substrate, and the polysilicon layer may be formed on theimpurity region using a deposition process or an epitaxial process. Themetal layer 282 may be formed of a cobalt (Co) layer. However, the metallayer 282 is not limited to a cobalt layer.

Referring to FIG. 6B, after forming the metal layer 282, a firstannealing process H1 may be applied to the metal layer 282 and thesemiconductor layer 280 to form a metal silicide layer 285. The firstannealing process H1 may be performed at a temperature of about 150degrees Celsius to about 1100 degrees Celsius. In FIG. 6A, if thesemiconductor layer 280 is a polysilicon layer and the metal layer 282is a cobalt (Co) layer, the metal silicide layer 285 may be a cobaltsilicide (CoSi_(x)) layer. However, the metal silicide layer 285 is notlimited to a cobalt silicide (CoSi_(x)) layer.

Referring to FIG. 6C, after forming the metal silicide layer 285,impurity ions Ion may be implanted into an upper portion of thesemiconductor layer 280 using an ion implantation process Im. FIG. 6Cillustrates as if the impurity ions Ion are implanted into an entiresurface of the semiconductor layer 280. However, FIG. 6C may merelycorrespond to an enlarged view of a portion of the semiconductor layer280. That is, the impurity ions Ion may be selectively implanted into aportion of the semiconductor layer 280 at a wafer level.

More specifically, a material layer acting as an ion implantation maskmay be formed on an entire surface of the metal silicide layer 285. Thematerial layer may be patterned using an etch process, thereby exposinga portion of the metal silicide layer 285. The exposed portion of themetal silicide layer 285 may be located on a desired (and/oralternatively predetermined) portion of the semiconductor layer 280where the impurity ions Ion are implanted. Subsequently, the impurityions Ion may be implanted into the desired (and/or alternativelypredetermined) portion of the semiconductor layer 280, as illustrated inFIG. 6C.

During the ion implantation process Im, the impurity ions Ion maypenetrate the metal silicide layer 285 and may reach the upper portionof the semiconductor layer 280. In such a case, the impurity ions Ionmay be disorderedly distributed within a desired (and/or alternativelypredetermined) depth from an interface between the semiconductor layer280 and the metal silicide layer 285. This may be due to a poordistribution and diffusion of the impurity ions in the ion implantationprocess Im.

Referring to FIG. 6D, after implanting the impurity ions ION, theimpurity ions Ion may be concentrated at the interface between thesemiconductor layer 280 and the metal silicide layer 285 by applying asecond annealing process H2 and an electric field E to the semiconductorlayer 280 and the metal silicide layer 285. The second annealing processH2 may be performed at a temperature of about 150 degrees Celsius toabout 1100 degrees Celsius. The electric field E may be created byapplying a voltage, which is equal to or lower than 10 volts, to ajunction between the metal silicide layer 285 and the semiconductorlayer 280. The voltage for creating the electric field E is not limitedto the aforementioned range.

As the impurity ions Ion are concentrated at the interface between thesemiconductor layer 280 and the metal silicide layer 285 by the secondannealing process H2 and the electric field E, the impurity ions Ion maybe redistributed to be thin under the interface between thesemiconductor layer 280 and the metal silicide layer 285. Accordingly, aconcentration of the impurity ions Ion under the interface between thesemiconductor layer 280 and the metal silicide layer 285 may increase,and the impurity ions Ion may be stably activated. As a result, acontact resistance value between the semiconductor layer 280 and themetal silicide layer 285 may be reduced.

FIGS. 7 and 8 are process flowcharts illustrating methods of fabricatingsemiconductor devices according to example embodiments using anannealing process accompanied with electric field.

Referring to FIG. 7, a method of fabricating a semiconductor deviceaccording to example embodiments may include implanting impurity ionsinto an impurity region in a substrate (see operation S410). Theimpurity ions may be implanted using an in-situ process. That is, theimpurity ions may be implanted into the impurity region while theimpurity region is formed. Alternatively, the impurity ions may beimplanted into the impurity region using a separate ion implantationprocess after the impurity region is formed. If the impurity ions areimplanted into the impurity region using the separate ion implantationprocess, a material pattern acting as an ion implantation mask may beformed on the impurity region and the impurity ions may be selectivelyimplanted into a portion of the impurity region using the materialpattern as an ion implantation mask, as described with reference to FIG.5 or 6C.

Subsequently, a metal silicide layer may be formed on the impurityregion and the impurity ions may be concentrated at an interface betweenthe metal silicide layer and the impurity region, using the same mannersas illustrated in FIG. 3. That is, a metal layer may be formed on theimpurity region (see operation S420) and the metal silicide layer may beformed using a first annealing process (see operation S430). Theimpurity ions may then be concentrated at an interface between the metalsilicide layer and the impurity region using a second annealing processand an electric field (see operation S440).

Referring to FIG. 8, a method of fabricating a semiconductor deviceaccording to example embodiments may include implanting impurity ionsinto an impurity region in a substrate (see operation S510). Theimpurity ions may be implanted using an in-situ process or a separateion implantation process, as described with reference to FIG. 7.

Subsequently, a metal silicide layer may be formed on the impurityregion and the impurity ions may be concentrated at an interface betweenthe metal silicide layer and the impurity region, using the same mannersas illustrated in FIG. 4. That is, a metal layer may be formed on theimpurity region (see operation S520), and an annealing process and anelectric field may be applied to the substrate including the metal layerto form a metal silicide layer and to concentrate impurity ions at aninterface between the impurity region and the metal silicide layer (seeoperation S530).

FIGS. 9A, 9B and 9C are cross-sectional views illustrating a method offabricating a semiconductor device shown in FIG. 8.

Referring to FIG. 9A, impurity ions Ion may be implanted into an activelayer 130 using an ion implantation process Im. The active layer 130 maybe a silicon (Si) substrate or a silicon germanium (SiGe) substrate. Forexample, the active layer 130 may correspond to an impurity region suchas a source/drain region that is formed by implanting the impurity ionsIon into a silicon (Si) substrate or a silicon germanium (SiGe)substrate. In a non-limiting example, the active layer 130 maycorrespond to a source/drain region that is formed by implantingimpurity ions into a portion of a silicon germanium (SiGe) substrate.

In a non-limiting example, the ion implantation process Im forimplanting the impurity ions Ion and an ion implantation process forforming a source/drain region in the active layer 130 may be performedseparately. In example embodiments, the impurity ions Ion may beimplanted into the active layer 130 using an in-situ process while theactive layer 130 is formed. In a non-limiting example, a projectionrange (Rp) of the ion implantation process Im for implanting theimpurity ions Ion may be shallower than a projection range (Rp) of theion implantation process for forming a source/drain region in the activelayer 130.

As described with reference to FIG. 6C, the impurity ions Ion may bedisorderedly distributed within a desired (and/or alternativelypredetermined) depth from a top surface of the active layer 130. Thismay be due to a poor distribution and diffusion of the impurity ions inthe ion implantation process Im.

Referring to FIG. 9B, after implanting the impurity ions Ion, a metallayer 142 may be formed on the active layer 130. The metal layer 142 maybe formed of, for example, a nickel (Ni) layer. The metal layer 142 mayreact with silicon atoms in the active layer 130 during an annealingprocess to form a metal silicide layer. If the metal silicide layer is anickel silicide (NiSi_(x)) layer, the annealing process may be performedat a relatively low temperature. For example, whereas a cobalt silicidelayer may be formed using an annealing process performed at a hightemperature over 800 degrees Celsius, a nickel silicide layer may beformed using an annealing process performed at a low temperature ofabout 400 degrees Celsius.

Referring to FIG. 9C, after forming the metal layer 142, an annealingprocess H accompanied with electric field E may be applied to thesubstrate including the metal layer 142 to form a metal silicide layer140 on the active layer 130 and to concentrate the impurity ions Ion atan interface between the active layer 130 and the metal silicide layer140. If the metal layer 142 is formed of a nickel (Ni) layer, the metalsilicide layer 140 may be a nickel silicide layer. The annealing processH may be performed at a temperature of about 150 degrees Celsius toabout 1100 degrees Celsius. The electric field E may be created byapplying a voltage, which is equal to or lower than 10 volts, to ajunction between the metal silicide layer 140 and the active layer 130.

As described above, according to example embodiments, the impurity ionsIon may be concentrated at the interface between the active layer 130and the metal silicide layer 140 by the electric field E while the metalsilicide layer 140 is formed by the annealing process H. As describedabove, if the metal layer 142 is formed of a nickel layer, the annealingprocess H for forming the metal silicide layer 140 (e.g., a nickelsilicide layer) may be performed at a low temperature of about 400degrees Celsius. However, the metal layer 142 is not limited to a nickellayer. For example, in example embodiments, the metal layer 142 may beformed of a cobalt layer. In such a case, the annealing process H forforming the metal silicide layer 140 (e.g., a cobalt silicide layer) maybe performed at a high temperature over 400 degrees Celsius.

As the impurity ions Ion are concentrated at the interface between theactive layer 130 and the metal silicide layer 140 by the annealingprocess H and the electric field E, the impurity ions Ion may beredistributed to be thin under the interface between the active layer130 and the metal silicide layer 140. Accordingly, a concentration ofthe impurity ions Ion under the interface between the active layer 130and the metal silicide layer 140 may increase, and the impurity ions Ionmay be stably activated. As a result, a contact resistance value betweenthe active layer 130 and the metal silicide layer 140 may be reduced.

FIGS. 10 and 11 are process flowcharts illustrating methods offabricating semiconductor devices on a substrate of a wafer levelaccording to example embodiments using an annealing process accompaniedwith electric field.

Referring to FIG. 10, a method of fabricating a semiconductor deviceaccording to example embodiments may include forming an impurity regionand a metal layer on a substrate (see operation S610). The substrate maybe a P-type or N-type substrate having a wafer form. The impurity regionmay be formed by implanting impurity ions into the substrate. The metallayer may be formed by depositing metal on the impurity region. Themetal layer maybe formed of, for example, a cobalt layer or a nickellayer, but is not limited thereto. In example embodiments, an isolationlayer or a gate structure may be additionally formed on the substratebefore the metal layer is formed.

An upper electrode for applying an electric field may be formed on themetal layer (see operation S620). The upper electrode may be formed of arefractory metal layer having an excellent process compatibility. Inaddition, the upper electrode may be formed to have a single-layeredstructure or a multi-layered structure. For example, the upper electrodemay be formed of a combination layer of a titanium (Ti) layer and atitanium nitride (TiN) layer. Alternatively, the upper electrode 150 maybe formed to further include a tungsten layer disposed on the Ti/TiNlayer. In example embodiments, before the upper electrode is formed, anannealing process may be applied to the metal layer and the impurityregion to form a metal silicide layer.

Subsequently, a heavily doped region may be formed in a lower portion ofthe substrate (see operation S630). The heavily doped region may beformed by implanting impurity ions into the lower portion of thesubstrate. For example, if the substrate is a P-type substrate, theheavily doped region may be formed by implanting boron ions into thelower portion of the substrate. In such a case, the heavily doped regionmay be formed to have an impurity concentration of at least 1×10¹⁹/cm³.For example, the heavily doped region 114 may be formed to have animpurity concentration of at least the impurity region may be formed tohave an impurity concentration in a range of at least 1×10¹⁹/cm³ to atleast 1×10²⁰/cm³. The heavily doped region may act as an ohmic contactlayer between the substrate and a lower electrode to be formed in asubsequent process. That is, the heavily doped region may be formed toreduce (and/or minimize) a voltage drop across the substrate and thelower electrode.

After forming the heavily doped region, the lower electrode may beformed on a surface of the heavily doped region opposite to the upperelectrode (see operation S640). The lower electrode may be formed of arefractory metal layer having an excellent process compatibility, likethe upper electrode. For example, the lower electrode may be formed of aTi/TiN layer.

Subsequently, a metal silicide layer may be formed on the impurityregion and the impurity ions in the impurity region may be concentratedat an interface between the metal silicide layer and the impurityregion, using an annealing process and an electric field (see operationS650). If the metal silicide layer is formed prior to formation of theupper electrode, no additional metal silicide layer may be formed at theoperation S650. The impurity ions may be implanted into the substrateusing an in-situ doping process while the impurity region is formed ormay be implanted into the impurity region using a separate ionimplantation process after the impurity region is formed and before themetal layer is formed. Meanwhile, if the metal silicide layer is formedbefore the upper electrode is formed, the impurity ions may be implantedafter the metal silicide layer is formed and before the upper electrodeis formed.

In order to form the metal silicide layer and concentrate the impurityions at the interface between the metal silicide layer and the impurityregion using the annealing process and the electric field, the substrateincluding the lower electrode may be loaded into an annealing chamberand the upper and lower electrodes may be respectively connected to bothterminals of a power source. In such a case, the upper and lowerelectrodes may be respectively connected to both terminals of a powersource so that a reverse biased voltage is applied across a Schottkyjunction between the metal silicide layer and the impurity region.

Referring to FIG. 11, a method of fabricating a semiconductor deviceaccording to example embodiments may include forming a polysilicon layeron an impurity region in a substrate (see operation S710). The substratemay be a P-type or N-type substrate having a wafer form. The impurityregion may be a source/drain region that is formed by implantingimpurity ions into the substrate at a high dose. The polysilicon layermay be formed on the impurity region using a deposition process or anepitaxial process. The polysilicon layer may constitute a buried contact(BC) of a semiconductor device such as a DRAM device. In exampleembodiments, an isolation layer or a gate electrode may be additionallyformed on the substrate before the polysilicon layer is formed.

A metal layer may be formed on polysilicon layer (see operation S720).The metal layer may be formed of, for example, a cobalt layer.

After forming the metal layer, a first annealing process may be appliedto the substrate including the metal layer to form a metal silicidelayer (see operation S730). The metal silicide layer may be a cobaltsilicide layer. The first annealing process may be performed at atemperature of about 150 degrees Celsius to about 1100 degrees Celsius.If the metal layer is formed of a cobalt layer, the first annealingprocess may be performed at a high temperature over 800 degrees Celsius.

Subsequently, an upper electrode, a heavily doped region and a lowerelectrode may be formed using the same or similar manners as describedwith reference to FIG. 10. That is, the upper electrode for applying anelectric field may be formed on the metal silicide layer (see operationS740), the heavily doped region may be formed in a lower portion of thesubstrate (see operation S750), and the lower electrode may be formed ona surface of the heavily doped region opposite to the upper electrode(see operation S760).

After forming the lower electrode, the impurity ions in the polysiliconlayer may be concentrated at an interface between the metal silicidelayer and the polysilicon layer using a second annealing process and anelectric field (see operation S770). The second annealing process may beperformed at a temperature of about 150 degrees Celsius to about 1100degrees Celsius, and electric field may be created by applying avoltage, which is equal to or lower than 10 volts, to a junction betweenthe metal silicide layer and the polysilicon layer.

FIG. 12 is a cross-sectional view illustrating a semiconductor device100 b of a wafer level to which electric field is applied according toexample embodiments.

Referring to FIG. 12, the semiconductor device 100 b may include anohmic contact layer 110, a substrate 120, an active layer 130, a metalsilicide layer 140, an upper electrode 150, an insulation layer 160 andgate electrodes 170.

The ohmic contact layer 110 may include a lower electrode 112 and aheavily doped region 114. The lower electrode 112 may be formed of arefractory metal layer having an excellent process compatibility. Forexample, the lower electrode 112 may be formed of a Ti/TiN layer. Theheavily doped region 114 may be formed by implanting impurity ions intoa lower portion of the substrate 120 at a high dose. For example, if thesubstrate 120 is a P-type substrate, the heavily doped region 114 may beformed by implanting boron ions into a lower portion of the substrate120 at a high dose. In example embodiments, the heavily doped region 114may be excluded from the ohmic contact layer 110 or may be regarded as aportion of the substrate 120.

The substrate 120 may be a P-type substrate or an N-type substrate. In anon-limiting example, the substrate 120 may be a P-type substrate. Morespecifically, the substrate 120 may be a P-type silicon germanium (SiGe)substrate.

The active layer 130 may include various impurity regions. Specifically,if the substrate 120 is a P-type substrate, the active layer 130 mayinclude an N-type well 132, an N-type heavily doped region 134 b in theN-type well 132, and P-type heavily doped regions 136 sd in the N-typewell 132. The active layer 130 may further include N-type heavily dopedregions 134 sd in the substrate 120, a P-type heavily doped region 136 bin the substrate 120, and an N-type halo region 138 disposed under theP-type heavily doped region 136 b.

The N-type well 132 may have an impurity concentration which is higherthan an impurity concentration of the substrate 120 and which is lowerthan impurity concentrations of the P-type heavily doped regions 136 sdand the N-type heavily doped region 134 b. For example, the N-type well132 may be formed by implanting phosphorus ions or arsenide ions intothe substrate 120 to have an impurity concentration of about 1×10¹⁵/cm³to about 2×10¹⁹/cm³. The N-type heavily doped region 134 b may be formedby implanting N-type impurity ions into the N-type well 132 at a highdose. For example, the N-type heavily doped region 134 b may be formedto have an impurity concentration of at least about 1×10²⁰/cm³. TheP-type heavily doped regions 136 sd may be formed by implanting P-typeimpurity ions into the N-type well 132 at a high dose. For example, theP-type heavily doped regions 136 sd may be formed to have an impurityconcentration of at least about 1×10²⁰/cm³. For example, the heavilydoped region 134 b and/or 136 sd may be formed to have an impurityconcentration in a range of at least 1×10²⁰/cm³ to at least 1×10²¹/cm³.

The N-type well 132, the N-type heavily doped region 134 b, and theP-type heavily doped regions 136 sd may constitute a P-channel MOS(PMOS) transistor. For example, the N-type heavily doped region 134 bmay act as a body contact region (or a body pick-up region) of the PMOStransistor, and the P-type heavily doped regions 136 sd may act assource/drain regions of the PMOS transistor. Meanwhile, the substrate120, the N-type heavily doped regions 134 sd, and the P-type heavilydoped region 136 b may constitute an N-channel MOS (NMOS) transistor.For example, the N-type heavily doped regions 134 sd may act assource/drain regions of the NMOS transistor, and the P-type heavilydoped region 136 b may act as a body contact region (or a body pick-upregion) of the NMOS transistor. As described above, the semiconductordevice 100 b may be configured to have a CMOS circuit including the PMOStransistor and the NMOS transistor. For example, the semiconductordevice 100 b may be configured to be a CMOS logic device.

The N-type halo region 138 may be formed in the substrate 120 to contacta lower portion of the P-type heavily doped region 136 b. If theannealing process accompanied with electric field is applied to thesemiconductor device 100 b, the P-type heavily doped region 136 b andthe metal silicide layer 140 on the P-type heavily doped region 136 bmay provide a forward biased Schottky junction. In such a case, aleakage current may flow through the forward biased Schottky junction.However, the N-type halo region 138 may limit and/or stop the leakagecurrent from flowing through the forward biased Schottky junction. TheN-type halo region 138 may be formed to provide a P-N junction with theP-type heavily doped region 136 b and to have a planar area that isgreater than a planar area of the P-type heavily doped region 136 b in aplan view.

The metal silicide layer 140 may be formed on each of the impurityregions 134 b, 134 sd, 136 b and 136 sd. The metal silicide layer 140may contact the impurity regions 134 b, 134 sd, 136 b and 136 sd toprovide Schottky junctions, and the Schottky junctions may beforward-biased or reverse-biased according to a direction of electricfields applied thereto. Current flowing through the Schottky junctionsand ohmic contact and the electric fields created across the Schottkyjunctions will be described more fully with reference to FIG. 13.

The upper electrode 150 may be formed on an entire top surface of thesubstrate including the PMOS transistor and the NMOS transistor and maybe electrically connected to the metal silicide layer 140. The upperelectrode 150 may be formed of a refractory metal layer having excellentprocess compatibility. In addition, the upper electrode 150 may beformed to have a single-layered structure or a multi-layered structure.For example, the upper electrode 150 may be formed of a combinationlayer of a titanium (Ti) layer and a titanium nitride (TiN) layer. Theupper electrode 150 may further include a tungsten layer disposed on theTi/TiN layer.

The insulation layer 160 may be formed of an oxide layer, a nitridelayer or an oxynitride layer. The insulation layer 160 may be formed tohave a single-layered structure or a multi-layered structure. Moreover,the insulation layer 160 may act as an isolation layer that electricallyinsulates elements such as the transistors from each other. The gateelectrodes 170 may be formed of a conductive layer. For example, thegate electrodes 170 may be formed of a metal layer or a polysiliconlayer. A gate dielectric layer may be disposed between each gateelectrode 170 and the active layer 130. Spacers 180 may be formed onsidewalls of the gate electrodes 170, and a capping layer may be formedon a top surface of each gate electrode 170. The gate dielectric layer,the spacers, the capping layer and the gate electrode 170 may constitutea gate structure.

FIG. 13 is an equivalent circuit diagram illustrating junctions in thesemiconductor device 100 b shown in FIG. 12.

Referring to FIGS. 12 and 13, the metal silicide layer 140 may contactthe P-type heavily doped regions 136 sd to provide a forward-biasedSchottky junction {circle around (2)} (p+SD/metal) in a PMOS transistorregion, and the metal silicide layer 140 may contact the N-type heavilydoped regions 134 b to provide a reverse-biased Schottky junction{circle around (3)} (n+/metal) in the PMOS transistor region. Meanwhile,an N/N+ junction (n-active/n+) may be present between the N-type well132 and the N-type heavily doped regions 134 b in the PMOS transistorregion. The N/N+ junction may be provided due to a Fermi leveldifference between the N-type well 132 and the N-type heavily dopedregions 134 b. A P/N (p+SD/n-active) junction may be provided betweenthe P-type heavily doped regions 136 sd and the N-type well 132 in thePMOS transistor region. In addition, a P/N junction (p-sub/n-active) maybe provided between the substrate 120 and the N-type well 132 in thePMOS transistor region.

In an NMOS transistor region, the metal silicide layer 140 may contactthe N-type heavily doped regions 134 sd to provide a reverse-biasedSchottky junction {circle around (4)} (n+/metal), and the metal silicidelayer 140 may contact the P-type heavily doped regions 136 b to providea forward-biased Schottky junction {circle around (5)} (p+/metal).Moreover, a P/N junction (p-sub/n+) junction may be provided between theN-type heavily doped regions 134 sd and the substrate 120 in the NMOStransistor region, and a P/P+ junction (p-sub/p+) may be present betweenthe substrate 120 and the P-type heavily doped regions 136 b in the NMOStransistor region. The P/P+ junction may be provided due to a Fermilevel difference between the substrate 120 and the P-type heavily dopedregions 136 b. Meanwhile, a P/N junction (n-halo/p+) may be providedbetween the N-type halo region 138 and the P-type heavily doped regions136 b in the NMOS transistor region.

A junction (p+/p-sub) may be provided between the heavily doped region114 and the substrate 120. The junction (p+/p-sub) may be provided dueto a Fermi level difference between the heavily doped region 114 and thesubstrate 120. A reverse-biased Schottky junction {circle around (1)}(p+/metal) may be provided between the heavily doped region 114 and thelower electrode 112. If an impurity concentration of the heavily dopedregion 114 is appropriately controlled, the reverse-biased Schottkyjunction {circle around (1)} (p+/metal) may exhibit almost an ohmiccontact characteristic. In such a case, a voltage drop across thereverse-biased Schottky junction {circle around (1)} (p+/metal) may bereduced (and/or minimized). For example, if the substrate 120 is aP-type substrate, boron ions may be implanted into the substrate 120 ata high dose to form the heavily doped region 114 having an impurityconcentration of at least about 1×10¹⁹/cm³. For example, the heavilydoped region 114 may be formed to have an impurity concentration of atleast the impurity region may be formed to have an impurityconcentration in a range of at least 1×10¹⁹/cm³ to at least 1×10²⁰/cm³.In such a case, the reverse-biased Schottky junction {circle around (1)}(p+/metal) may exhibit almost an ohmic contact characteristic.

If the annealing process accompanied with the electric field is appliedto the semiconductor device 100 b, current may flow in a directionindicated by an arrow in the semiconductor device 100 b. That is, duringthe annealing process accompanied with the electric field, most of avoltage applied to the semiconductor device 100 b may be applied to thereverse-biased Schottky junctions {circle around (3)} and {circle around(4)} to concentrate the impurity ions in the vicinity of thereverse-biased Schottky junctions {circle around (3)} and {circle around(4)} because the reverse-biased Schottky junction {circle around (1)}exhibits almost an ohmic contact characteristic. Meanwhile, during theannealing process accompanied with the electric field, an influence ondopants in the forward-biased Schottky junction {circle around (21)} maybe neglected because a reverse bias is applied to the P/N(p+SD/n-active) junction connected head-to-head to the forward-biasedSchottky junction {circle around (2)} to cause a hole passivationphenomenon or a hole accumulation phenomenon. In addition, during theannealing process accompanied with the electric field, an influence ondopants in the forward-biased Schottky junction {circle around (5)} maybe neglected because the N-type halo region 138 suppresses the leakagecurrent that flows through the P-type heavily doped region 136 b. As aresult, during the annealing process accompanied with the electricfield, the leakage current flowing through the forward-biased Schottkyjunctions {circle around (2)} and {circle around (5)} may be neglected.

FIG. 14 is a cross-sectional view illustrating a semiconductor devicefabricated according to example embodiments.

Referring to FIG. 14, after the annealing process accompanied with theelectric field is performed, the lower electrode 112 and the upperelectrode 150 illustrated in FIG. 13 may be removed to realize asemiconductor device, for example, a logic device including a CMOScircuit.

The upper electrode 150 may be formed to include a Ti/TiN layer and atungsten (W) layer. In such a case, an entire portion of the upperelectrode 150 may not be removed. For example, a node separating processfor the upper electrode 150 may be performed to leave portions of theupper electrode 150 on the meal silicide layers 140 and the gateelectrodes 170. The left portions of the upper electrode 150 may be usedas metal electrodes 150 a which are electrically connected to the mealsilicide layers 140. The node separating process for forming the metalelectrodes 150 a may be performed using a chemical mechanical polishing(CMP) process or a lithography process.

In example embodiments, the lower electrode 112 may not be removed. Ifthe lower electrode 112 remains, a passivation layer having aninsulation property may be formed to cover the lower electrode 112.

FIG. 14 basically illustrates a planar type CMOS structure, butinventive concepts are not limited thereto. For example, in exampleembodiments, the semiconductor device according to the embodiment may berealized to have a three-dimensional CMOS structure includingthree-dimensional transistors such as fin type field effect transistors(fin-FETs). More specifically, if the semiconductor device is realizedto have a CMOS structure including fin-FETs, the impurity regions (e.g.,the active layer) may be formed to have a fin-shaped body protrudingfrom a substrate and the gate structure may be formed to cover twoopposite sidewalls and a top surface of the fin-shaped body. In order toapply the annealing process accompanied with the electric field to thethree-dimensional semiconductor device including the fin-FETs, a heavilydoped region may be formed in a lower portion of a substrate and anN-type halo region may be formed under a P-type heavily doped regionconstituting a forward-biased Schottky junction in an NMOS transistorregion. A metal silicide layer may also be formed between an activelayer and a metal electrode, and impurity ions may be concentrated at aninterface between the active layer and the metal silicide layer toreduce a contact resistance value.

FIG. 15A is a plan view illustrating a dynamic random access memory(DRAM) device 200 according to example embodiments. FIGS. 15B, 15C and15D are cross-sectional views taken along lines I-I′, II-II′ andIII-III′ of FIG. 15A, respectively.

Referring to FIGS. 15A, 15B, 15C and 15D, the DRAM device 200 mayinclude a plurality of active regions (ACT) 216. The plurality of activeregions (ACT) 216 may be defined by an isolation layer 214 formed in asubstrate 210. As design rules of semiconductor devices are reduced, theactive regions (ACT) 216 having a bar shape may be disposed to beparallel with a diagonal direction as illustrated in FIG. 15A. Aplurality of parallel word lines (WL) 224 may be disposed on the activeregions (ACT) 216 to extend in a second direction (e.g., an x-axisdirection) and to intersect the active regions (ACT) 216. A plurality ofparallel bit lines (BL) 245 may be disposed on the word lines (WL) 224to extend in a first direction (e.g., a y-axis direction) and tointersect the word lines (WL) 224.

The substrate 210 may be a P-type substrate or an N-type substrate andmay have the same configuration as described with reference to FIG. 2.The isolation layer 214 may be formed of a single-layered insulationlayer or a multi-layered insulation layer including an exteriorinsulation layer 214A and an interior insulation layer 214B. The activeregions (ACT) 216 may be separated from each other by the isolationlayer 214, and heavily doped regions may be disposed in upper regions ofthe active regions (ACT). For example, source regions 216S and drainregions 216D may be disposed in upper regions of the active regions(ACT).

A heavily doped region 212 may be formed in a lower portion of thesubstrate 210. The heavily doped region 212 may be formed to provideohmic contact while an annealing process accompanied with electric fieldis performed. The heavily doped region 212 may be formed by implantingimpurity ions into the substrate 210, and a conductivity type of theimpurity ions may be determined according to a conductivity type of thesubstrate 210.

The word lines 224 may be formed to be buried in the substrate 210, andtop surfaces of the word lines 224 may be located at a level which islower than a top surface of the substrate 210. A bottom surface of eachof the word lines 224 may have an uneven profile, as illustrated in FIG.15C. Saddle fin-FETs may be formed on the active regions 216. In exampleembodiments, the word lines 224 may be formed to include at least oneselected from the group consisting of a titanium (Ti) layer, a titaniumnitride (TiN) layer, a tantalum (Ta) layer, a tantalum nitride (TaN)layer, a tungsten (W) layer, a tungsten nitride (WN) layer, a titaniumsilicon nitride (TiSiN) layer and a tungsten silicon nitride (WSiN)layer.

A gate dielectric layer 222 may be disposed between the word lines 224and the active regions 216. The gate dielectric layer 222 may be formedto include at least one selected from the group consisting of a siliconoxide (SiO) layer, a silicon nitride (SiN) layer, a silicon oxynitride(SiON) layer, an oxide/nitride/oxide (O/N/O) layer and a high-kdielectric layer. The high-k dielectric layer means a dielectric layerhaving a dielectric constant which is higher than a dielectric constantof a silicon oxide layer. In example embodiments, the gate dielectriclayer 222 may be formed of a dielectric layer having a dielectricconstant of about 10 to about 25.

A buried insulation layer 226 may be formed on the word lines 224, and atop surface of the buried insulation layer 226 may be substantiallycoplanar with a top surface of the substrate 210. The buried insulationlayer 226 may be formed to include at least one selected from the groupconsisting of a silicon oxide (SiO) layer, a silicon nitride (SiN) layerand a silicon oxynitride (SiON) layer.

An interlayer insulation pattern 230 may be formed on the substrate 210.The interlayer insulation pattern 230 may be formed to include a siliconoxide layer 232 and a silicon nitride layer 234. In example embodiments,the interlayer insulation pattern 230 may be formed of only a siliconoxide layer. For example, the interlayer insulation pattern 230 may beformed of a tetra-ethyl-ortho-silicate (TEOS) layer, a high densityplasma (HDP) oxide layer, or a borophosphosilicate glass (BPSG) layer.

The DRAM device 200 may include various contacts on the active regions216.

For example, the DRAM device 200 may include direct contacts (DC) 235,buried contacts (BC) 280 and landing pads (LP) 290 a which are disposedon the active regions 216. The direct contacts 235 may electricallyconnect the active regions 216 to the bit lines 245, and the buriedcontacts 280 may electrically connect the active regions 216 to lowerelectrodes (not shown) of capacitors.

The direct contacts 235 may contact the source regions 216S of theactive regions 216, and lower portions of the direct contacts 235 may besurrounded by spacers. The spacers may be formed of a material which isdifferent from the isolation layer 214.

A plurality of parallel bit line structures 240 may be disposed on theinterlayer insulation pattern 230 and the direct contacts 235 to extendin the second direction (e.g., the x-axis direction). Each of the bitline structures 240 may include the bit lines 245 and a capping line 248covering a top surface of the bit line 245. The bit lines 245 may beelectrically connected to the direct contacts 235.

In example embodiments, the bit lines 245 may be formed to include atleast one selected from the group consisting of a doped semiconductorlayer, a metal layer, a metal nitride layer and a metal silicide layer.Each of the bit lines 245 may be formed to have a single-layeredstructure or a multi-layered structure. For example, each of the bitlines 245 may be formed to include a polysilicon layer 242, a tungstennitride layer 244 and a tungsten layer 246 which are sequentiallystacked.

Multi-layered spacers 250 may be formed to surround sidewalls of the bitline structures 240. Each of the multi-layered spacers 250 may includean insulation liner 252, a first spacer 254 and a second spacer 256. Inexample embodiments, each of the multi-layered spacers 250 may includeonly one or two among the insulation liner 252, the first spacer 254 andthe second spacer 256. In some other embodiments, each of themulti-layered spacers 250 may include an air spacer.

The buried contacts 280 may be disposed between the multi-layeredspacers 250, and bottom surfaces of the buried contacts 280 mayrespectively contact the drain regions 216D of the active regions 216.The buried contacts 280 may be formed of a polysilicon layer, forexample, a doped polysilicon layer. Each of the buried contacts 280 mayinclude a barrier layer (not shown) such as a Ti/TiN layer. A metalsilicide layer 285 may be formed on each of the buried contacts 280. Themetal silicide layer 285 may be formed of, for example, a cobaltsilicide (CoSi_(x)) layer, but the metal silicide layer 285 is notlimited to a cobalt silicide (CoSi_(x)) layer.

If the DRAM device 200 is scaled down to increase its integrationdensity, contact areas between the buried contacts 280 and the activeregions 216 may be reduced. Thus, conductive landing pads 290 a may beintroduced into the DRAM device 200 to increase (and/or maximize) thecontact areas between the buried contacts 280 and the active regions 216as well as contact areas between the buried contacts 280 and lowerelectrodes (not shown) of capacitors. The landing pads 290 a may bedisposed between the buried contacts 280 and the active regions 216 orbetween the buried contacts 280 and the lower electrodes of capacitors.In a non-limiting example, the landing pads 290 a may be disposedbetween the buried contacts 280 and the lower electrodes of thecapacitors. More specifically, the landing pads 290 a may be disposed onthe metal silicide layers 285, respectively. Accordingly, if the landingpads 290 a are introduced into the DRAM device 200, contact resistancevalues between the active regions 216 and the lower electrodes of thecapacitors may be reduced.

Each of the landing pads 290 a may include a barrier layer (not shown)and a metal layer on the barrier layer. In example embodiments, thebarrier layer of each landing pad 290 a may be formed of a Ti/TiN layer,as described above. Moreover, the metal layer of each landing pad 290 amay be formed of a tungsten layer.

Elements indicated by a reference numeral “270” may correspond to fencesthat are disposed between the buried contacts 280 arrayed in the firstdirection (e.g., the y-axis direction), and the fences 270 may be formedof an insulation layer such as an oxide layer or a nitride layer. Inaddition, an element indicated by a reference numeral “278” maycorrespond to a capping insulation layer 278 that covers the landingpads 290 a. Capacitors (not shown) may be formed to penetrate thecapping insulation layer 278 and may be electrically connected to thelanding pads 290 a.

In the DRAM device 200, the direct contacts 235 may be disposed oncentral portions of the active regions 216, and the buried contacts 280may be disposed on both ends of the active regions 216. Because theburied contacts 280 are disposed on both ends of the active regions 216,the landing pads 290 a may be disposed to be adjacent to both ends ofthe active regions 216 and may be disposed to partially overlap with theburied contacts 280.

The word lines 224 may be formed to be buried in the substrate 210 andmay be disposed to cross the active regions 216 between the directcontacts 235 and the buried contacts 280. As illustrated in FIG. 15A,each of the active regions 216 may be disposed to intersect two adjacentword lines 224, and the active regions 216 may be arrayed to be parallelwith a diagonal direction in a plan view of FIG. 15A. Thus, the wordlines 224 may intersect the active regions 216 at a non-right angle.

The direct contacts 235 may be disposed to be line symmetric withrespect to the X-axis or the Y-axis. In addition, the buried contacts280 may also be disposed to be line symmetric with respect to the X-axisor the Y-axis. Thus, the direct contacts 235 and the buried contacts 280may be disposed on straight lines which are parallel with the firstdirection (e.g., the y-axis direction) or the second direction (e.g.,the x-axis direction). Unlike the direct contacts 235 and the buriedcontacts 280, the landing pads 290 a may be arrayed in a zigzag fashionalong the first direction (e.g., the y-axis direction) in which the bitlines 245 extend.

Although FIGS. 15A, 15B, 15C and 15D illustrate the DRAM device 200,inventive concepts are not limited to the DRAM device. As describedabove, the heavily doped region 212 may be formed in a lower portion ofthe substrate 210, and the metal silicide layer 285 may be formed oneach of the buried contacts 280. The buried contacts 280 may be formedof, for example, a polysilicon layer. In example embodiments, if theannealing process accompanied with electric field is applied to the DRAMdevice 200, impurity ions may be concentrated at interfaces between theburied contacts 280 and the metal silicide layer 285. As a result,contact resistance values between the buried contacts 280 and the metalsilicide layer 285 may be reduced to improve characteristics of the DRAMdevice 200.

FIGS. 16A and 16B are schematic diagrams illustrating a DRAM deviceaccording to example embodiments.

Referring to FIGS. 16A and 16B, the semiconductor layer 280 maycorrespond to a buried contact and may be formed of a polysilicon layer.The metal silicide layer 285 may be disposed on the semiconductor layer280 and may be formed of a cobalt silicide layer. As illustrated inFIGS. 16A and 16B, a first grain boundary Bg1 may exist in thesemiconductor layer 280, and a second grain boundary Bg2 may exist inthe metal silicide layer 285.

If only an annealing process is applied to the semiconductor layer 280and the metal silicide layer 285 without any electric field, impurityions Ion in the semiconductor layer 280 may leak through the secondgrain boundary Bg2 as illustrated in FIG. 16A. As a result, the impurityions Ion may not be accumulated or concentrated at an interface betweenthe semiconductor layer 280 and the metal silicide layer 285 to increasea contact resistance value between the semiconductor layer 280 and themetal silicide layer 285.

In contrast, if an annealing process accompanied with an electric fieldis applied to the semiconductor layer 280 and the metal silicide layer285, most of the impurity ions Ion in the semiconductor layer 280 may beaccumulated or concentrated at the interface between the semiconductorlayer 280 and the metal silicide layer 285 as illustrated in FIG. 16B.Thus, the contact resistance value between the semiconductor layer 280and the metal silicide layer 285 may be reduced.

FIGS. 17A and 17B are cross-sectional views illustrating a principle ofa silicide as dopant source (SADS) technology used in fabrication ofsemiconductor devices according to example embodiments.

Referring to FIGS. 17A and 17B, the SADS technology may mean atechnology for forming a metal silicon layer 140 on an active layer 130and for supplying dopants in the metal silicon layer 140 to the activelayer 130 using an annealing process H. The SADS technology may berealized with an ion implantation process. If the SADS technology isapplied to the metal silicon layer 140 and the active layer 130,impurity ions may be concentrated at an interface between the metalsilicon layer 140 and the active layer 130 to make a thin junction.Thus, a contact resistance value between the metal silicon layer 140 andthe active layer 130 may be reduced.

In example embodiments, the SADS technology may be realized togetherwith the annealing process accompanied with electric field. That is, theannealing process accompanied with electric field may be performed byforming a metal silicide layer, applying an annealing process, applyingan ion implantation process, and applying an electric field. As aresult, impurity ions may be concentrated at an interface between theactive layer 130 and the metal silicide layer 140, and the impurity ionsmay be stably activated. Thus, the concentration and the stableactivation of the impurity ions may lead to decrease in a contactresistance value between the active layer 130 and the metal silicidelayer 140, as described above.

FIG. 18 a schematic view illustrating an apparatus 1000 used infabrication of semiconductor devices according to example embodiments,and FIG. 19 is a graph illustrating a voltage and a temperature appliedto a wafer loaded into the apparatus shown in FIG. 18.

Referring to FIGS. 18 and 19, the apparatus 1000 may include anannealing chamber 1100, a supporter 1200, a temperature/voltagecontroller 1300, a heat source 1400, a power source 1500, a lead probeunit 1600, and a temperature sensor 1700.

The annealing chamber 1100 may basically have the same or similarconfiguration as general annealing chambers. However, the annealingchamber 1100 may further include some elements to create electric fieldwhich is applied to semiconductor devices loaded therein. The annealingchamber 1100 may isolate an inside space thereof from an externalenvironment. The annealing chamber 1100 may include a chamber wallseparating the inside space thereof from the external environment andinternal elements disposed in the chamber wall.

A wafer 100 may be loaded into the annealing chamber 1100, and the wafer100 may be put on the supporter 1200 which is installed in the annealingchamber 1100. That is, the wafer 100 may be supported by the supporter1200 in the annealing chamber 1100. Accordingly, a planar area of thesupporter 1200 may be greater than a planar area of the wafer 100.However, in example embodiments, a planar area of the supporter 1200 maybe equal to or less than a planar area of the wafer 100. The supporter1200 may be formed of or coated by a metal material having low heatconductivity and an excellent heat resistant property. For example, thesupporter 1200 may be formed of or coated by a nickel chrome (NiCr)material.

The temperature/voltage controller 1300 may control a temperature and avoltage which are applied to the wafer 100. For example, thetemperature/voltage controller 1300 may control a temperature applied tothe wafer 100 so that a temperature profile T of the wafer 100 has atrapezoidal shape as the time elapses. Moreover, the temperature/voltagecontroller 1300 may also control a voltage applied to the wafer 100 sothat a voltage signal V having a pulse waveform is applied to the wafer100 while the wafer 100 is heated to exhibit the temperature profile T.However, the temperature and the voltage applied to the wafer 100 arenot limited to the temperature profile T and the voltage signal Villustrated in FIG. 19. For example, in example embodiments, a voltagesignal having a square waveform may be applied to the wafer 100 during adesired (and/or alternatively predetermined) period while the wafer 100is heated. That is, a constant voltage may be applied to the wafer 100during the desired (and/or alternatively predetermined) period while thewafer 100 is heated to have a constant temperature.

The heat source 1400 may be disposed over the wafer 100 put on thesupporter 1200. The heat source 1400 may include a plurality of lamps.The heat source 1400 may emit heat toward the wafer 100, and thetemperature/voltage controller 1300 may control operations of the heatsource 1400 to adjust the temperature of the wafer 100. The temperaturesensor 1700 may be disposed under the wafer 100 to control thetemperature of the wafer 100. More specifically, the temperature sensor1700 may detect and measure the temperature of the wafer 100, andinformation on the measured temperature of the wafer 100 may betransmitted to the temperature/voltage controller 1300. Thetemperature/voltage controller 1300 may receive the temperatureinformation from the temperature sensor 1700 and may control on/offoperations of the lamps constituting the heat source 1400 to control thetemperature of the wafer 100. The temperature sensor 1700 may beelectrically connected to the temperature/voltage controller 1300 totransmit the temperature information on the wafer 100 to thetemperature/voltage controller 1300.

Although FIG. 18 illustrates an example in which the temperature sensor1700 penetrates the supporter 1200, inventive concepts are not limitedthereto. For example, in example embodiments, the temperature sensor1700 may be disposed on a top surface of the supporter 1200 andinput/output signal lines of the temperature sensor 1700 may extendalong a sidewall of the supporter 1200 to reach the temperature/voltagecontroller 1300.

The power source 1500 may apply a voltage to the wafer 100 through thelead probe unit 1600. The power source 1500 may be electricallyconnected to the temperature/voltage controller 1300, and operations ofthe power source 1500 may be controlled by the temperature/voltagecontroller 1300.

The lead probe unit 1600 may include upper lead probes 1610 and lowerlead probes 1630. The upper lead probes 1610 may be electricallyconnected to a positive terminal of the power source 1500, and the lowerlead probes 1630 may be electrically connected to a negative terminal(e.g., a ground terminal) of the power source 1500. Although FIG. 18illustrates an example in which the upper and lower lead probes 1610 and1630 penetrate the supporter 1200, inventive concepts are not limitedthereto. For example, in example embodiments, the upper and lower leadprobes 1610 and 1630 may be disposed on sidewalls of the supporter 1200.

The upper lead probes 1610 may extend to contact a lower electrode 112which is formed on a top surface of the wafer 100, and the lower leadprobes 1630 may extend to contact an upper electrode 150 which is formedon a bottom surface of the wafer 100.

The upper and lower lead probes 1610 and 1630 may be formed of a metalmaterial having a low heat conductivity and an excellent heat resistantproperty. For example, the upper and lower lead probes 1610 and 1630 maybe formed of a nickel chrome (NiCr) material. In addition, each of theupper and lower lead probes 1610 and 1630 may have a shape that issuitable for contacting the lower electrode 112 or the upper electrode150. Upper ends of the upper lead probes 1610 may be disposed betweenthe wafer 100 and the heat source 1400 to apply the voltage to the wafer100. In such a case, upper ends of the upper lead probes 1610 have to bedesigned to reduce (and/or minimize) a shadow effect that the upper endsof the upper lead probes 1610 block the heat emitted from the heatsource 1400. In example embodiments, each of the upper ends of the upperlead probes 1610 may be designed to have a pin shape.

While some example embodiments of inventive concepts has beenparticularly shown and described, it will be understood that variouschanges in form and details may be made therein without departing fromthe spirit and scope of the following claims.

1. (canceled)
 2. A semiconductor device comprising: a substrate; upperimpurity regions in upper portions of the substrate; metal electrodeselectrically connected to the upper impurity regions; metal silicidelayers between the metal electrodes and the upper impurity regions; anda lower impurity region in a lower portion of the substrate, wherein thesubstrate is a P-type substrate; the upper impurity regions include NMOSimpurity regions of an NMOS transistor; and the NMOS impurity regionsinclude a P-type heavily doped region in the substrate and an N-typehalo region under the P-type heavily doped region.
 3. The semiconductordevice of claim 2, wherein the substrate includes an N-type well, theupper impurity regions include P-type heavily doped source and drainregions of a PMOS transistor and N-type heavily doped source and drainregions of the NMOS transistor, the PMOS transistor includes an N-typeheavily doped body contact region in the N-type well, and the lowerimpurity region is a P-type heavily doped lower impurity region.
 4. Thesemiconductor device of claim 2, wherein the semiconductor device is alogic device, the upper impurity regions include source/drain regionsand body contact regions, and the metal silicide layers correspond tointerfacial layers between the source/drain regions and the metal layersas well as between the body contact regions and the metal layers.
 5. Anapparatus comprising: a supporter configured to support a wafer; atemperature/voltage controller configured to control a temperature and avoltage applied to the wafer; a heat source over the supporter, the heatsource configured to emit heat toward the supporter and be controlled bythe temperature/voltage controller; a power source configured to apply avoltage to the wafer and be controlled by the temperature/voltagecontroller; an upper lead probe connected to the power source andconfigured to contact a top surface of the wafer; and a lower lead probeconnected to a ground terminal of the power source and configured tocontact a bottom surface of the wafer.
 6. The apparatus of claim 5,wherein the wafer includes a lower electrode on a top surface thereofand an upper electrode connected to a bottom surface thereof, and theupper lead probe contacts the lower electrode, and the lower lead probecontacts the upper electrode.
 7. The apparatus of claim 5, wherein thetemperature/voltage controller is configured to apply programmed heatand voltage to the wafer through the heat source and the power source ina concurrent time domain.
 8. The apparatus of claim 5, furthercomprising: a temperature sensor under the wafer, wherein thetemperature/voltage controller is configured to control an operation ofthe heat source based on temperature information that is outputted fromthe temperature sensor.
 9. The apparatus of claim 5, wherein theapparatus is configured to concentrate impurity ions in the wafer at aninterface between an active layer and a metal suicide layer in thewafer, based on emitting heat from the heat source and applying thevoltage generated from the power source to the wafer.
 10. Asemiconductor device comprising: a substrate; upper impurity regions inupper portions of the substrate; metal electrodes electrically connectedto the upper impurity regions; metal silicide layers between the metalelectrodes and the upper impurity regions; and a lower impurity regionin a lower portion of the substrate, wherein impurity ions areconcentrated at an interface between the upper impurity regions and themetal silicide layer.
 11. The semiconductor device of claim 4, whereinthe impurity regions comprise silicon (Si), and the metal silicide layercomprises nickel silicide (NiSix).
 12. The apparatus of claim 5, whereinthe wafer comprises a plurality of semiconductor devices, and each ofthe semiconductor devices is fabricated to comprise a substrate, upperimpurity regions in upper portions of the substrate, metal electrodeselectrically connected to the upper impurity regions, metal silicidelayers between the metal electrodes and the upper impurity regions, anda lower impurity region in a lower portion of the substrate.
 13. Thesemiconductor device of claim 10, wherein the substrate is a P-typesubstrate; the upper impurity regions include NMOS impurity regions ofan NMOS transistor; and the NMOS impurity regions include a P-typeheavily doped region in the substrate and an N-type halo region underthe P-type heavily doped region.
 14. The semiconductor device of claim10, wherein the substrate is a P-type substrate, the substrate includesan N-type well, the upper impurity regions include P-type heavily dopedsource and drain regions of a PMOS transistor and N-type heavily dopedsource and drain regions of an NMOS transistor, the PMOS transistorincludes an N-type heavily doped body contact region in the N-type well,the NMOS transistor includes a P-type heavily doped body contact regionin the substrate and an N-type halo region under the P-type heavilydoped region in the substrate, and the lower impurity region is a P-typeheavily doped lower impurity region.
 15. The semiconductor device ofclaim 10, wherein the semiconductor device is a logic device, the upperimpurity regions include source/drain regions and body contact regions,and the metal silicide layers correspond to interfacial layers betweenthe source/drain regions and the metal layers as well as between thebody contact regions and the metal layers.